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power management & multimarket datasheet rev 3.0, 08/20/2016 ir3883 800khz 3a easy sup ir buck ? synchronous buck regulator
ir3883 sup ir buck ? synchronous buck regulator product overview datasheet 2 rev 3.0 08/20/2016 1 product overview figure 1-1 ir3883 part number configuration code features ? wide input voltage range (2.5v-14v) with an external vcc ? single input voltage range (4.5v to 14v) ? continuous 3a load capability ? 800khz switching frequency ? 10ua supply current at shutdown ? easy sup ir buck ? engine stable with ceramic capacitors and no external compensation ? enhanced light load efficiency with reduced switching frequency and diode emulation ? forced continuous conduction mode option ? thermally compensated peak over-current protection with three selectable levels ? internal soft-start ? enable input ? pre-bias start up ? thermal shut down ? power good output ? precision reference voltage (0.5v+/-0.6%) ? small size 3mmx3mm qfn ? lead-free, halogen-free and rohs6 compliant description the ir3883 sup ir buck ? is an easy-to-use, fully integrated and highly efficient monolithic dc/dc regulator. the on-chip pwm controller and mosfets make ir3883 a space-efficient solution, providing accurate power delivery. the ir3883 employs an enhanced stabilit y (easy) engine that makes it stable with cera mic capacitors without compensation. ir3883 can operate in forced continuous conduction mode (fccm) or can enter diode emulation mode during light loads to save power. with ultra-light loads, ir3883 can enter a low quiescent current mode making it ideal for standby power supplies. it features important protection functions, such as pre-bias startup, internal soft-start, hiccup over- current protection and thermal shutdown to give required system level securi ty in the event of fault conditions. applications ? server and computing ? storage applications ? communications infrastructure ? general dc-dc converters ? distributed point of load power architectures table 1-1 ordering information part number package type standard pack part number form quantity ir3883 pqfn 3 mm x 3 mm tape and reel 3000 IR3883MTRPBF ir3883 pbf tr m lead free tape and reel package type
ir3883 sup ir buck ? synchronous buck regulator basic application datasheet 3 rev 3.0 08/20/2016 2 basic application figure 2-1 ir3883 basic application circuit figure 2-2 ir3883 performance curves boot vcc fb gnd pgnd sw pgood pgood en/fccm v ir3883 sup ir buck ? synchronous buck regulator block diagram datasheet 4 rev 3.0 08/20/2016 3 block diagram figure 3-1 simplified block diagram pwm gate drive logic adaptive on-time generator + - soft start control logic zcross pv in fault vcc se t fb vin boot sw pgnd vo pvin en/ fccm gnd pwm comp vcc vcc current limit control zero cross detection ldrvin hdrv ldrv ldrvin ldrvin fccm_en ov fault fault ov fccm vc c thermal shut-down ov detection fb ov ss ov fault internal reference inductor current ripple emulator + vref ocset hdrvin po r hdrvin + po r pg nd + enable ldo pgood po r
ir3883 sup ir buck ? synchronous buck regulator pinout diagram and pin description datasheet 5 rev 3.0 08/20/2016 4 pinout diagram and pin description figure 4-1 pinout diagram: pqfn 3 mm x 3 mm (top view) table 4-1 pin description pin no. name pin type function 1 vin s input supply to the internal ldo. 2 vcc s input bias for the internal control circuitry and driver. supplied by an internal ldo or an external vcc voltage. a 2. 2uf ceramic capacitor must be used between vcc and the power ground (pgnd). 3 ocset i over current protection (ocp) limit set point. three user selectable ocp limits are available by floating this pin, connecting it to vcc or connecting it to pgnd. 4 gnd s signal ground for internal reference and control circuitry. 5 en/fccm i multifunction pin: (1) enab le pin to turn on and off the ic. (2) enable diode emulation (de) mode operation when en/fccm voltage is lower than fccm stop threshold, or forced continuous conduction mode (fccm) operation, when en/ffcm voltage is higher than fcc start threshold. 6 pgood o power good status output pin is open drain. connect a pull up resistor of 50k ? from this pin to vcc or an external bias voltage. 7 fb i output voltage feedback pin. connect th is pin to the output of the regulator via a resistor divider to set the output voltage. 8 vo i vo sense pin. connect this pin directly to the output of the regulator to set the on-time. 9 boot i supply voltage for the high-side driver. connect this pin to the sw node of the regulator through a bootstrap capacitor. 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 pvin pgnd sw boot pvin pgnd sw sw vo fb pg en/ fccm gnd ocset vcc vin exposed pad
ir3883 sup ir buck ? synchronous buck regulator pinout diagram and pin description datasheet 6 rev 3.0 08/20/2016 10, 11, 12 sw o switch node. this pin is connected to the output inductor. 13, 14 pgnd s power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 15, 16 pvin s input supply for the power stage. exposed pad - exposed pad needs to be connected to pgnd with pcb layout design. thermal via holes can be placed on the exposed pad to aid thermal dissipation. table 4-1 pin description pin no. name pin type function
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 7 rev 3.0 08/20/2016 5 specifications 5.1 absolute maximum ratings stresses beyond those listed in table 5-1 may cause permanent damage to th e device. these are stress ratings only and functional operation of th e device at these or any other condit ions beyond those indicated in the operational sections of the s pecifications are not implied. note: 1. must not exceed 6v. 2. pgnd pin and gnd pin are connected together. 3. maximum sw node voltage should not exceed the absolute maximum rating defined in table 5-1. note: 4. ja is measured with components mounted on a high effect ive thermal conductivity test board in free air table 5-1 absolute maximum ratings parameter min max units conditions pvin, vin, en/fccm to pgnd -0.3 16 v 2. 3. vcc to pgnd -0.3 6 v 2. boot to pgnd -0.3 22 v (dc) 2. -0.3 24 v (ac, 10ns) 2. sw to pgnd -0.3 16 v (dc) 2. -4.0 18 v (ac, 10ns) 2. boot to sw -0.3 vcc + 0.3 v 1. v o , fb to gnd -0.3 6 v (dc) 2. -0.3 6.5 v (ac, 10us) 2. ocset, pgood to gnd -0.3 6 v 2. pgnd to gnd -0.3 0.3 v table 5-2 thermal information parameter value / units condition junction-to-ambient thermal resistance ja 40 o c/w 4. junction to pcb thermal resistance j - pcb 6 o c/w junction to case top thermal resistance j - ctop 38 o c/w storage temperature range -55 o c to 150 o c junction temperature range -40 o c to 150 o c
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 8 rev 3.0 08/20/2016 5.2 recommended op erating conditions note: 5. vin is connected to vcc to bypass the internal ldo. 6. vin is connected to pvin. for single -rail applications with pvin=vin=4.5v-5.5 v, vcc (the internal ldo output voltage) is in dropout mode. please refer to the ap plication information in the internal ldo and the over current protection sections. 5.3 electrical characteristics unless otherwise specified, these specifications apply over, 5.5v < vin = pvin < 14v, 0c < t j < 125c. typical values are specified at ta = 25c. table 5-3 recommended operating conditions symbol parameter min max units condition pvin input voltage range with external vcc 2.5 14 v 5. 3. pvin, vin input voltage range with internal ldo 5.5 14 v 6. 3. vcc supply voltage range 4.5 5.5 v 3. v o output voltage range 0.5 5 v i o continuous output current range 0 3 a t j operating junction temperature -40 125 o c table 5-4 electrical characteristics symbol parameter test conditions min typ max units power stage r ds(on)_top top switch v boot - vsw= 5.2v, tj =25c - 82 106.4 m ? r ds(on)_bot bottom switch vcc = 5.2v, tj =25c - 26 33.9 m ? boot diode forward voltage i boot = 10ma 200 300 mv supply current i in(standby) vin supply current (standby) en = low - 1.8 10 a i in(static) vin supply current (static) en = 2v, no switching - 137 200 a i in(dyn) vin supply current (dynamic) en = high, fs = 800khz, vin = 12v -4.55.5ma soft-start ss rate soft-start ramp rate 0.16 0.2 0.24 mv/s feedback voltage v fb feedback voltage - 0.5 v accuracy 0c ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 9 rev 3.0 08/20/2016 note: 7. hot and cold temperature performance is assured via corr elation using statistical qualit y control. no t tested in production. 8. ensured by design but not tested in production. t off(min) minimum off-time v fb = 0v, tj = 25c 240 320 ns internal regulator (ldo) v cc ldo output voltage 5.5v < v in < 14v, 0a - 5.5ma 4.9 5.2 5.4 v 4.5v < v in < 5.5v, 0a - 5.5ma 4.4 - - v v ln line regulation 5.5v < v in < 14v, 5.5ma - - 30 mv v ld load regulation 0a - 5.5ma - - 100 mv i short short circuit current - 90 - ma thermal shutdown thermal shutdown 8. -145- o c hysteresis 8. -25- o c under voltage lockout v cc _uvlo_ start v cc start threshold v cc rising trip level 4 4.2 4.4 v v cc _uvlo_ stop v cc stop threshold v cc falling trip level 3.6 3.8 4.1 v enable_high enable threshold ramping up 1.14 1.2 1.36 v enable_low ramping down 0.9 1 1.06 v r en input impedance 500 1000 1500 k ? v fccm_start fccm start threshold 2.6 - - v v fccm_stop fccm stop threshold - - 2.3 v current limit i oc current limit threshold 0c ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 10 rev 3.0 08/20/2016 5.4 typical operating characteristics -40c to +125c figure 5-1 typical operation characteristics (set 1 of 3) 0 20 40 60 80 100 120 140 \ 40 \ 20 0 20 40 60 80 100 120 140 (m ? ) te m pe rat ure ? (c) r ds(on) ? at ? vcc=5.1v control ? fet sync ? fet 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 \ 40 \ 20 0 20 40 60 80 100 120 140 ( a) te m p e ratu re ? (c) i in (standby) 4.55 4.60 4.65 4.70 4.75 4.80 \ 40 \ 20 0 20 40 60 80 100 120 140 (ma) te m p e r a t u re ? (c) i in (dyn) 80 90 100 110 120 130 140 150 \ 40 \ 20 0 20406080100120140 ( a) te m p e ra t u re ? (c) i in (static) 4.4 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 \ 40 \ 20 0 20406080100120140 vcc ? (v) te m p e ra t u r e ? (c) vcc ? @ ? icc ? = ? 5.5ma vin ? = ? 5.5v vin=4.5v 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 5.3 5.35 5.4 \ 40 \ 20 0 20406080100120140 (v) te m p e ratu re ? (c) vcc ? voltage ? ? = ? 0ma ? icc=5.5ma 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 \ 40 \ 20 0 20406080100120140 (v) te m p e ra t u re ? (c) vcc ? uvlo vcc ? uvlo ? start vcc ? uvlo ? stop 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 1.25 1.30 \ 40 \ 20 0 20 40 60 80 100 120 140 (v) te m p e rat ure ? (c) en ? uvlo enable ? uvlo ? start enable ? uvlo ? stop
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 11 rev 3.0 08/20/2016 figure 5-2 typical operation characteristics (set 2 of 3) 2.50 3.00 3.50 4.00 4.50 5.00 5.50 \ 40 \ 20 0 20406080100120140 (a) te m pe rature ? (c) iocp 2.38 2.4 2.42 2.44 2.46 2.48 2.5 2.52 \ 40 \ 20 0 20406080100120140 (v) te m p e r at ure ? (c) fccm ? start/stop ? threshold fccm ? start fccm ? stop 575 580 585 590 595 600 605 610 615 620 625 \ 40 \ 20 0 20406080100120140 (mv) te m p e ratu re ? (c) ovp_vth 420 425 430 435 440 445 450 455 \ 40 \ 20 0 20 40 60 80 100 120 140 (mv) te m p e ra t u re ? (c) power ? good ? threshold vpg(on) vpg(lower) ocset ? = ? gnd ocset ? = ? floating ocset ? = ? vcc 105 106 107 108 109 110 111 112 113 114 115 \ 40 \ 20 0 20 40 60 80 100 120 140 on \ time ? (ns) te m pe ra ture ? (c) on \ time ? pvin ? =12v, ? vo ? = ? 1.05v 700 750 800 850 900 950 1000 0 0.5 1 1.5 2 2.5 3 fsw ? (khz) iout ? (a) fsw ? vs. ? iout ? at ? room ? temperature vin=12v, ? vo=3.3v, ? l ? = ? xal5030 ?\ 222, ? co ? = ? 2x ? 22uf ? 3.15 3.2 3.25 3.3 3.35 3.4 3.45 00.511.522.53 vo ? (v) io ? (a) load ? regulation ? at ? room ? temperature pvin=12v, ? vo=3.3v, ? fsw=800khz, ? l=2.2uh, ? co=2x22uf fccm, ? cff=220pf dem, ? cff ? = ? 220pf 497.00 498.00 499.00 500.00 501.00 502.00 503.00 \ 40 \ 20 0 20 40 60 80 100 120 140 (mv) te mp e rature ? (c) vfb
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 12 rev 3.0 08/20/2016 figure 5-3 typical operation characteristics (set 3 of 3)
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 13 rev 3.0 08/20/2016 5.5 12v typical efficiency and power loss curves pv in = 12v, v cc = internal ldo, i o = 0a-3a, room temperature, no air fl ow. note that the efficiency and power loss curves include the losses of ir3883 , the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the output voltages in the efficiency measurement. figure 5-4 12v efficiency and all power losses in cluding inductor losses and losses of input and output capacitors in forced continuous conduction mode. figure 5-5 diode emulation mode improves efficiency at light load (12vin) table 5-5 inductor list for ir3883 12v efficiency measurement vout (v) lout (h) p/n dcr (m ? ) 1.0 1.0 xel4030-102 8.89 1.2 1.0 xel4030-102 8.89 1.8 1.5 xel4030-152 15.1 2.5 2.2 xal5030-222 13.2 3.3 2.2 xal5030-222 13.2 5 3.3 xal5030-332 21.2 60 65 70 75 80 85 90 95 100 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 efficiency ? (%) io ? (a) ir3883 ? efficiency ? @ ? pvin ? =12v ? and ? fccm 5v 3.3v 2.5v 1.8v 1.2v 1.0v 0 0.2 0.4 0.6 0.8 1 1.2 00.511.522.533.5 power ? losses ? (w) io ? (a) ir3883 ? power ? losses ? @ ? pvin ? =12v ? and ? fccm 5v 3.3v 2.5v 1.8v 1.2v 1.0v 60 65 70 75 80 85 90 95 100 0.02 0.12 0.22 0.32 0.42 0.52 0.62 0.72 0.82 efficiency ? (%) io ? (a) ir3883 ? efficiency ? @ ? pvin ? =12v ? and ? dem 5v 3.3v 2.5v 1.8v 1.2v 1.0v 0 0.05 0.1 0.15 0.2 0.25 0.3 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 power ? losses ? (w) io ? (a) ir3883 ? power ? losses ? @ ? pvin ? =12v ? and ? dem 5v 3.3v 2.5v 1.8v 1.2v 1.0v
ir3883 sup ir buck ? synchronous buck regulator specifications datasheet 14 rev 3.0 08/20/2016 5.6 5v typical efficien cy and power loss curves pv in = v in = v cc = 5v, i o = 0a-3a, room temperature, no air flow. no te that the efficiency and power loss curves include the losses of ir3883, the inductor losses and the losses of the input and output capacitors. the table below shows the inductors used for each of the out put voltages in the efficiency measurement. figure 5-6 5v efficiency and all power losses including inductor losses and losses of input and output capacitors in forced continuous conduction mode. table 5-6 inductor list for ir3883 5v efficiency measurement vout (v) lout (h) p/n dcr (m ? ) 0.9 1.0 xel4030-102 8.89 1.0 1.0 xel4030-102 8.89 1.2 1.0 xel4030-102 8.89 1.8 1.5 xel4030-152 15.1 2.5 1.5 xel4030-152 15.1
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 14 rev 3.0 08/20/2016 6 theory of operation the ir3883 is an easy-to-use, fully integrated and high ly efficient monolithic dc/dc regulator. the on-chip pwm controller and mosfets make ir3883 a space-effici ent solution, providing accurate power delivery. the ir3883 offers two different operation modes: forced continuous conduction mode (fccm) and diode emulation mode (dem). with fccm, the device always op erates as a synchronous buck converter with a pseudo constant switching frequency of 800 khz and small output voltage ri pples. in dem, the synchronous fet is turned off when the inductor current drops to zero, which provides better efficiency at the light load. 6.1 easy sup ir buck ? engine the ir3883 uses the enhanced stability (easy) engine that comprises co nstant on-time contro l with proprietary internal ramp compensation to offer stability across a wide range of conditions. unlike conventional cot devices, which usually require a ce rtain amount of output ripple voltages to ensure the stability, the ir3883 includes proprietary internal ramp compensation, facilitating the use of low esr ceramic output capacitors without resorting to th e injection of external ripple voltage. in addition, the internal ramp implements the input voltag e feedfoward feature, which helps to preserve the same loop response with a wide input voltage range. the operation of ir3883 is described as follows. the output voltage of the regulator is fed to the fb pin through a resistor divider. combined with the proprietary internal ramp, the fb voltage is then compared to an internal reference voltage. if the combined voltage is lower than the reference voltage, the control fet is turned on for a fixed duration to charge the output capacitor. when the on-time of the control fet is finished, the synchronous fet is turned on. in fccm, synchronous fet stays on t ill the combination of fb vo ltage and the internal ramp drops below the reference volt age and a new pwm pulse is initiated. in dem, synchronous fet will be turned off when the inductor current drops to zero. 6.2 pseudo constant switching frequency the ir3883 operates with a pseudo constant frequency of 800 khz within the recommended operation range. to achieve the constant switching frequency, the on-time of the control fet is automatic ally adjusted for different input and output voltages. the on-time is determined by the ratio of the voltages at v o pin and pv in pin, and can be calculated as follows: 6.3 soft-start the ir3883 has an internal digital soft-start circuit to co ntrol the output voltage rise time, and to limit the current surge at the start-up. to ensure correct start-up, the so ft-start sequence initiates when enable and vcc voltages rise above their uvlo thresholds and generate the powe r on ready (por) signal. the internal soft-start signal linearly rises at the rate of 0.2mv/us. the nominal vout start-up time is fixed, and is equal to: the over-current protection (ocp) and over-voltage protec tion (ovp) are enabled during the soft-start to protect the device for any short circuit or over voltage condition. figure 6-1 illustrates the theoreti cal operation waveforms during the start-up. k pv v t in on 800 1 0 = ms us mv v t start 5 . 2 / 2 . 0 5 . 0 = =
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 15 rev 3.0 08/20/2016 figure 6-1 theoretical waveforms during soft-start 6.4 en/fccm en/fccm is a multi-function pin. it can be used to: ? on/off the ir3883 ? select the operation mode: fccm or dem ? implement under-voltage lockout of the input voltage when en/fccm voltage is higher than the enable_high thresh old, 1.2v typical, the ir3883 is turned on with dem. in order to operate in fccm, the en/fccm voltage ne eds to be above 2.6v. the enable/fccm thresholds are designed to be compatible with 3.3v logic. the ir3883 has a precise enable_high threshold voltage, which is internally moni tored by the under-voltage lockout (uvlo) circuit. as shown in configuration_1 in figure 6-2 , the input of the enable pin can be derived from the pvin voltage by a set of resistive divider, ren1 and ren2. by selecting different divider ratios, users can program the uvlo threshold voltage. the bus voltage uvlo is a very desirable feat ure. it prevents the ir3883 from regulating at pvin lower than the desired voltage level. for some space constrained designs, the en/fccm pin c an be directly connected to pvin without using the external resistor dividers. the en/fccm pin should not be left floating. a pull down resi stor in the range of tens of kilo ohms is recommended. cofiguration_2 and configuration_3 in figure 6-2 include the connections of en/fccm without using the external resistor divider. figure 6-3 illustrates the theoreti cal start-up waveforms. figure 6-2 en/fccm configurations por pgood internal ? softstart fb 0.9*vref 0. 5v r en1 r en2 pvin en/fccm ir3883 pvin pvin en/fccm ir3883 pvin vin vin vcc vcc 5v en/fccm ir3883 pvin vin vcc configuration_1: single supply with internal ldo, adjustable pvin uvlo and optional fccm or dem configuration_2: single supply with internal ldo and fccm operation configuration_3: single supply with 5v input, external vcc and fccm operation
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 16 rev 3.0 08/20/2016 figure 6-3 en/fccm theoretical start-up waveforms 6.5 pre-bias start-up the ir3883 is able to start up into a pre-charged ou tput without causing oscillations and disturbances of the output voltage. when ir3883 starts up with a pre-biased output voltage, both control fet and synch fet are kept off till the internal soft-start sign al exceeds the fb voltage. during pre-bias start-up, pgood sign al is held low till the first gate signal for control fet is generated. 6.6 internal low dropout (ldo) ir3883 has an integrated low dropout ldo regulator, provid ing the dc bias voltage for the internal circuitry. the typical ldo output voltage is 5.2v. a 2.2uf low esr ce ramic capacitor is required to be placed close to the vcc pin. for internally biased single rail operation, vin pi n should be connected to pvin pin, as shown in the first 2 configurations of figure 6-2 . if an external bias voltage is used, vin pin should be connected to vcc pin to bypass the internal ldo, as shown in figure 6-4 . to minimize the standby current, the internal ldo is disa bled when the enable of ir3883 is below the enable_high threshold. figure 6-4 use an external bias voltage pvin= vin=12v vcc enable >1.2v fb 0v 0v 0v 0v vcc_uvlo 0v 90% of vref pgood pgood stays at logic low start-up with enable up after pvin and vin. pgood is pulled up to an external supply. start-up with pvin, vin and enable tied together. pgood is pulled up to an external supply vcc fb 0v 0v 0v vcc_uvlo 0v 90% of vref pgood pgood stays at logic low pvin=vin=enable=12v en threshold pvin en/fccm ir3883 pvin vin vcc ext vcc
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 17 rev 3.0 08/20/2016 6.7 over current protection ir3883 offers three selectable over current limits us ing ocset pin. the over current protection (ocp) is performed by sensing the peak in ductor current through the rds(on) of the sync mosfet. this method enhances the converter?s efficiency, reduces cost by elim inating a current sense resistor and any layout related noise issues. the current limit is pre-se t internally and is compensated according to the ic temperature to minimize the ocp limit variation induced by temperature. howe ver, ocp limits are not vcc compensated. if vcc drops below the regulation, ocp limits are also reduced. ocp circuit senses the current of the sync mosfet at the end of 100ns after control fet is turned off. if the current exceeds the ocp limit, pgood an d soft-start signal will be pulled low. sync fet remains on till the current is decreased to zero, then ir3883 enters hiccup mode. both control fet and sync fet remain off during the hiccup blanking time. after the hiccup blanking time expires, ir3883 will try to restart. if the over current fault is still detected, the pr eceding actions will be repeated. ir3883 stays in the hiccup mode till the over current fault is removed. ocp is activated in start-up also. figure 6-5 illustrates the operation of ocp. figure 6-5 ocp with hiccup mode illustrations 6.8 minimum on-time and off-time the minimum on-time refers to the shortest time for contro l fet to be reliably turned on . typically, it is 20ns for ir3883. the minimum off-time refers to the minimum time durat ion in which the sync fet stays on for each switching cycle. the minimum off-time is needed for ir3883 to charge the bootstrap capacitor and to monitor the current of the sync fet for ocp. for high duty-cycle applicatio ns, it is importan t to make sure the desired off-time is larger than the minimum off- time specified in the electrical table. in real applications, the switching fr equency can increase with the load current, in order to compensate for the power losses induced voltage drop in the circuitry. the following formula could be used to estimate the off-time when the conduction losses of power stage and dcr losses of the inductor are considered. inductor current current limit hdrv ldrv pgood 100ns hiccup blanking time
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 18 rev 3.0 08/20/2016 where r ds(on)ctrl and r ds(on)sync are the r ds(on) of the control fet and sync fet respectively. dcr is the dc resistance of the inductor. to ensure a proper operation, toff should meet the following criterion. where (minimum off - time) max = 320ns. please note that the actual toff is usually smaller th an the calculated value as shown above because the switching losses, losses on the pcb losses etc. are not consi dered in the calculation. 6.9 over voltage protection (ovp) the ir3883 senses the voltage at fb pin for over-voltage protection (ovp) . when fb voltage exceeds the ovp threshold for the duration longer than the output ov protection delay (typical value is 5 s), ovp circuitry is tripped. control fet is turned off immediatel y and pgood is pulled low. sync fet is turned on to discharge the output capacitor, till the fb voltage drops below the ovp threshold. once ovp is tripped, contro l fet remains latched off till a reset is pe rformed by cycling either vcc voltage or enable signal. figure 6-6 illustrates the operation of over voltage protection. figure 6-6 operation of over voltage protection 6.10 power good output the pgood pin is the open drain of an internal nfet and needs to be externally pulled high through a pull-up resistor. pgood signal is high when three criteria are satisfied. 1. enable and vcc voltages are a bove their respective thresholds. 2. no fault occurs including over curren t, over voltage and over temperature. 3. vout is within regulation. 0 ) ( 0 0 ) ( 0 ) ( ) ( i dcr r v i dcr r v v t t sync on ds ctrl on ds in on off + + + ? ? = max time) - off mimum ( > off t 120%v ref 90%v ref ovp delay =5us 115%v ref ldrv hdrv pgood fb v ref
ir3883 sup ir buck ? synchronous buck regulator theory of operation datasheet 19 rev 3.0 08/20/2016 in order to detect if vout is in regulation, pgood co mparator continuously monitors the fb voltage. when fb voltage ramps up above the upper threshold ? 90% of vref, pgood signal is pulled high. when fb voltage ramps down below the lower threshold ? 85% of vref, pgood signal is pulled low. figure 6-7 illustrates the pgood upper and lower thresholds. for pre-biased start-up, pgood is not active until the first gate signal of the control fe t is initiated. ir3883 also integrates an additional pfet in parallel to the pgood nfet, as shown in figure 3-1 . this pfet allows pgood signal to stay at logic low when the bias voltage of ir3883 is low, and/or the en is low, but the external pgood bias voltage still presents. please refer to figure 6-3 . a 50k ? pull-up resistor is needed for 3.3v pgood bias voltage to maintain pgood low when ir3883 is disabled. figure 6-7 power good thresholds 6.11 over temper ature protection temperature sensing is provided insi de ir3883. the over temperature protection (otp) threshold is typically set to 145 o c. when otp threshold is exceeded, both mosfets are tu rned off, and the internal soft-start is reset. the internal ldo is still in oper ation when otp is tripped. automatic restart is initiated when t he sensed temperature drops below the ot p threshold. the hysteresis of the otp threshold is 25 o c. 85%v ref 90%v ref 90%v ref fb pgood v ref
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 20 rev 3.0 08/20/2016 7 application information the following key parameters shall be used as an example for typical ir3883 applications. the application circuit is shown in figure 7-1 . ?pv in = 12v (10%) ?v o = 3.3v ?i o = 3a ?v o ripple voltage = 1% of v o ? transient response = 3% of v o (for 30% load transient) 7.1 enabling ir3883 to enable ir3883 in diode emulation mode (dem), the voltage at en/fccm pin should be higher than the enable threshold, but lower than fccm stop threshold. if a resi stor divider is used to generate the enable voltage from pvin as shown in figure 6-2 configuration 1, the resistor divider can be selected as follows. where pv in(min) and pv in(max) are the minimum and maximum input voltages respectively. to enable ir3883 in fccm, the voltage at en/fccm pin should be no less than the fccm start threshold. the en/fccm pin can be connected directly to pvin, or a resistor divider can be used. following criterion should be satisfied when selecting the resistor divider for fccm. 7.2 input capacitor selection without input capacitors, the pulse curr ent of control fet is directly from the input supply po wer. due to the impedance on the cable, the pulse current can cause dist urbance on the input voltage and potential emi issues. the input capacitors filter the pulse current of the control fet, resulting in almost constant current from the input supply. the input capacitors should be selected to tolerate the input pulse curren t, and to reduce the input voltage ripple. the rms value of the input ripple current can be expressed by: where: i rms is the rms value of the input capacitor current. i o is the output current. d is the duty cycle to meet the requirement of the input ripple voltage, the minimum input capa citance can be calculated as follows. 36 . 1 2 1 2 (min) + en en en in r r r pv 3 . 2 2 1 2 (max) + en en en in r r r pv 6 . 2 2 1 2 (min) + en en en in r r r pv ) 1 ( 0 d d i i rms ? = in v v d 0 =
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 21 rev 3.0 08/20/2016 where ? v in(max) is the maximum allowable peak-to-peak input ripple voltage. ceramic capacitors are recommended as input capacitors due to low esr, esl and high rms current capability. in addition, a bulk capacitor is recommended if the inpu t supply is not located close to the voltage regulator. 7.3 inductor selection the inductor is selected based on output power, operat ing frequency and efficiency requirements. a low inductor value causes large ripple current, re sulting in the smaller size, faster response to a load transient but lower efficiency and high output noise. ge nerally, the desired peak-to-peak ripple current in the inductor ( ? i) is found between 20% and 50% of the output current. the saturation current of the inductor is desired to be hi gher than the over current limit. an inductor with soft- saturation characteristic is recommend ed. for some core material, inductor saturation current may decrease as the increase of temperature. so it is important to check the inductor saturation current at the high temperature for the buck converter, the inductor value for the desire d operating ripple current can be determined using the following relation: where: pv inmax = maximum input voltage v o = output voltage ? i lmax = maximum inductor peak-to-peak ripple current f s = switching frequency t onmin = on-time when pv in = pv inmax d min = minimum duty cycle 7.4 output capacitor selection to ensure the loop stability, a minimu m of 22uf output capacitor is suggested. the volt age ripple an d transient requirements determine the output capacitor selection. please refer to table 7-1 . the following formula calculates the peak-to-peak output voltage ripple due to the inductor ripple current charging the output capacitor. therefore, where: ? v omin = minimum allowable peak-peak output ripple voltage. (max) 0 (min) ) 1 ( in sw in v f d d i c ? > min max max on l o in t i l v pv = ? s on f d t min min = ; s l o in f i d v pv l ? = max min max ) ( max 0 min in v v d = ; sw l f c i v = 0 max 0 8 sw l f v i c > min 0 max 0 8
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 22 rev 3.0 08/20/2016 ? i lmax = maximum inductor ripple current the esr and esl of the output capacitors, as well as t he parasitic resistance or in ductance due to pcb layout, can also contribute to the output voltage ripple. for most applications, it is suggeste d to use multi-layer ceramic capacitor (mlcc) as output capacitors for their low esr, esl and small size. to meet the transient response requirements, the outpu t capacitors should also meet the following criterion. where ? v ol_max is the max allowable v o deviation during the load transient. ? i omax is the maximum step load current. please note that the impact of esl, esr, cont rol loop response, transient load slew rate, and pwm latency is not considered in the calculation shown above. extra capacitance is usually needed to meet the transient requirements. 7.5 output voltage programming output voltage can be programmed with an external voltage divider. the fb voltage is compared to an internal reference voltage of 0.5v. the divider ratio is set to provide 0.5v at the fb pin when the output is at its desired value. the calculation of the feedback resistor divider is shown below. where r fb1 and r fb2 are the top and bottom feedback resistors. r fb2 is recommended not to be greater than 20k ? , in order to avoid the interferen ce with the internal circuitry. 7.6 feedforward capacitor a small mlcc capacitor, cff, can be placed in parallel with the top feedback resistor, r fb1 , to improve the transient response. as a general rule of thumb, for a fixed r fb1 of 16.5k ? , 100pf can be used for v o less than 1.8v, and 220pf for v o equal to/higher than 1.8v. please refer to table 7-1 . 7.7 bootstrap capacitor selection for most applications, a 0.1uf ceramic capacitor is recommended for bootstrap capacitor placed between sw node and boot pin. 7.8 v cc bypass capacitor a 2.2uf ceramic capacitor must be placed between v cc and gnd. 0 max _ 0 2 max 0 0 2 v v i l c l > ) 1 ( 2 1 0 fb fb ref r r v v + =
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 23 rev 3.0 08/20/2016 7.9 recommended configurations table 7-1 lists recommended configurations fo r a few commonly used output voltages. note: 1. the output capacitors are selected to meet 1% outp ut ripple voltage and 3% undershoot/overshoot at 30% of max load transient with 2.5a/s slew rate. more output capacitors might be needed for more stringent transient load requirements. please note that 22 uf is rated capacitance at 0v dc bias voltage. 2. r fb1 and r fb2 are the top and bottom feedback resistor respec tively, shown as r6 and r7 respectively in figure 7-1 . 3. the selection of l is based on 20% - 50% of max output current. table 7-1 recommended configurations vin (v) i omax (a) v o (v) r fb1 (k ? ) note 2. r fb2 (k ? ) note 2. l ( h ) note 3. c ff (pf) minimum c o ( f) note 1. 53 0.9 15.0 18.7 1.0 100 2 x 22 f 1.0 16.5 16.5 1.2 16.5 11.8 1.8 16.5 6.34 1.5 220 2.5 16.5 4.12 12 3 0.9 15.0 18.7 1.0 100 2 x 22 f 1.0 16.5 16.5 1.2 16.5 11.8 1.8 16.5 6.34 1.5 220 2.5 16.5 4.12 2.2 3.3 16.5 2.94 5.0 16.0 1.78 3.3 12 1.5 0.9 15.0 18.7 2.2 100 2 x 22 f 1.0 16.5 16.5 1.2 16.5 11.8 1.8 16.5 6.34 3.3 220 2.5 16.5 4.12 4.7 3.3 16.5 2.94 5.0 16.0 1.78
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 24 rev 3.0 08/20/2016 table 7-2 list of inductors l ( h ) part number (p/n) manufacturer i sat (a) dcr (m ? ) size (l x w x h) (mm) 1.0 xel4030 - 102 coilcraft 9.0 8.89 4 x 4 x 3.1 1.0 xfl5030 - 102 coilcraft 6.5 4.2 5.28 x 5.48 x 3.1 1.0 cmle053t - 1r0 delta 11 8.4 4.85 x 4.7 x 2.8 1.0 spm5030 - 1r0 tdk 8.5 11.44 5.2 x 5.0 x 3.0 1.5 xel4030 - 152 coilcraft 8.5 15.1 4 x 4 x 3.1 1.5 cmlb051h - 1r5 delta 9 23 5.4 x 5.75 x 1.8 2.2 xal5030 - 222 coilcraft 9.2 13.2 5.28 x 5.48 x 3.1 2.2 cmle053t - 2r2 delta 8.2 21 4.9 x 5.2 x 3.0 3.3 xal5030 - 332 coilcraft 8.7 21.2 5.28 x 5.48 x 3.1 3.3 cmle053t - 3r3 delta 7.3 29.7 4.9 x 5.2 x 3.0 4.7 xal5030 - 472 coilcraft 6. 36 5.28 x 5.48 x 3.1 4.7 cmle063t - 4r7 delta 8 23.6 6.8 x 7.3 x 3.0
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 25 rev 3.0 08/20/2016 7.10 application diagram and bill of materials figure 7-1 application circuit for a 12v to 3.3v, 3a point of load converter table 7-3 suggested bill of materials for the application circuit qua ntity part ref. value descripti on part number manufactur er 1c12.2 f cap cer 2.2uf 16v 10% x5r 0402 grm155r61c225ke44d murata 1c2 1 f cap cer 1uf 16v 10% x5r 0402 grm155r61c105ke01d murata 2 c4, c5 0.1 f cap cer 0.1uf 16v 10% x7r 0402 grm155r71c104ka88d murata 2 c6, c7 22 f cap cer 22uf 16v 20% x5r 0805 c2012x5r1c226m125ac tdk 2 c10, c11 22 f cap cer 22uf 6.3v x5r 20% 0805 c2012x5r0j226m tdk 1 c9 220pf cap cer 220pf 50v 10% x7r 0402 gcm155r71h221ka37d murata 1l12.2 h 5.28x5.48x3mm, dcr=13.2m, isat=7.2a xal5030-222 coilcraft 2 r2, r5 49.9k res smd 49.9k ohm 1% 1/10w 0402 erj-2rkf4992x panasonic 1r3 16.5k (fccm) res smd 16.5k ohm 1% 1/10w 0402 erj-2rkf1652x panasonic 8.06k (dem) res smd 8.06k ohm 1% 1/10w 0402 erj-2rkf8061x panasonic 1 r4 0 res smd 0.0 ohm jumper 1/10w erj-2ge0r00x panasonic 1 r7 2.94k res smd 2.94k ohm 1% 1/10w 0402 erj-2rkf2941x panasonic 2 r6, r10 16.5k res smd 16.5k ohm 1% 1/10w 0402 erj-2rkf1652x panasonic 1 u1 ir3883 3mmx3mm 3a pol regulator IR3883MTRPBF infineon
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 26 rev 3.0 08/20/2016 7.11 typical operating waveforms pv in = v in = 12.0v, v o =3.3v, i o =0a - 3a, no airflow, room temperature figure 7-2 start up at 3a load, enable = en/fccm (ch 1 :pv in , ch 2 :v o , ch 3 :p good , ch 4 :v cc ) figure 7-3 start up at 0a load, enable = en/dem (ch 1 :pv in , ch 2 :v o , ch 3 :p good , ch 4 :v cc )
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 27 rev 3.0 08/20/2016 figure 7-4 start up at 0a load with a pre-bias voltage of 2.64v, fccm (ch 1 :sw, ch 2 :v o , ch 3 :p good , ch 4 :en) figure 7-5 start up at 0a load with a pre-bias voltage of 2.64v, dem (ch 1 :sw, ch 2 :v o , ch 3 :p good , ch 4 :en)
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 28 rev 3.0 08/20/2016 figure 7-6 fccm, sw node, 3a figure 7-7 diode emulation mode, sw node, 0.3a
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 29 rev 3.0 08/20/2016 figure 7-8 fccm, v o ripple, 3a load, v out figure 7-9 dem, v o ripple, 0.3a load
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 30 rev 3.0 08/20/2016 figure 7-10 short circuit (hiccup) recover (fccm) (ch 1 =sw, ch 2 =v out , ch 3 =p good , ch 4 =i o ) figure 7-11 enter ocp hiccup mode (fccm) (ch 1 =sw, ch 2 =v out , ch 3 =p good , ch 4 =i o )
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 31 rev 3.0 08/20/2016 figure 7-12 transient response, 0a to 3.0a step, fccm (ch 2 =v out , ch 4 = i out , undershoot: -43mv, overshoot: 49mv) figure 7-13 transient response, 0.03a to 3.0a step, dem (ch 2 =v out , ch 4 = i out , undershoot: -31mv, overshoot: 61mv)
ir3883 sup ir buck ? synchronous buck regulator application information datasheet 32 rev 3.0 08/20/2016 7.12 ir3883 thermal image figure 7-14 ir3883 thermal image thermal image of the board at vin = 12v, vo = 3.3v, io = 3a, no airflow; ir3883 =55oc, l= 46oc, amb = 25oc
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 33 rev 3.0 08/20/2016 8 layout recommendations the pinout of ir3883 makes it easy to route the pcb la yout. general pcb design gu idelines should be followed to achieve the best performance. ? bypass capacitors, including input/out put capacitors and vcc bypass capacito r, should be placed as close as possible to the corresponding pins. ? sw node area should be minimized and be limited to the top layer only ? output voltage should be sensed with a separated trace directly from the output capacitor. the sensing trace should be away from the inductor and sw node to avoid the interference of switching noises. ? analog ground and power ground are connected through a single point connection. ? the feedback resistor divider should be connected to the analog ground. ? the exposed pad can be connected to power ground pl ane through via holes to aid thermal dissipation. ? wide copper polygons are desired for input and output power connections in favor of power losses reduction and thermal dissipation. sufficient via holes should be used to connect the power traces between different layers. figure 8-1 irdc3883 demo board layout ? top layer pvin pgnd vo pgnd single point connection between agnd and pgnd
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 34 rev 3.0 08/20/2016 figure 8-2 irdc3883 demo board layer ? signal layer 1 figure 8-3 irdc3883 demo board layout ? signal layer 2 pgnd to aid thermal dissipation , exposed pad is connected to pgnd through 4 via holes feedback trace is away from l and sw node . pgnd
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 35 rev 3.0 08/20/2016 figure 8-4 irdc3883 demo board layer ? bottom layer 8.1 pcb metal and component placement evaluations have shown that the best overall performance is achieved using the substrate/pcb layout as shown in following figures. pqfn devices should be placed to an accuracy of 0.050mm on both x and y axes. self- centering behavior is highly dependent on solders and processes and experiments should be run to confirm the limits of self-centering on specific processes. for further information, please refer to sup ir buck ? multi-chip module (mcm) po wer quad flat no-lead (pqfn) board mounting application note.? (an1132) pvin pgnd vo
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 36 rev 3.0 08/20/2016 figure 8-5 pcb metal pad sizing and spacing (all dimensions in mm)
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 37 rev 3.0 08/20/2016 8.2 stencil design stencils for pqfn can be used with th icknesses of 0.100-0.250mm (0.004-0.010?). stencils thinner than 0.100mm are unsuitable because they deposit in sufficient solder paste to make good solder joints with the ground pad; high reductions sometimes create similar problems. stencils in the range of 0.125mm-0.200mm (0.005-0.008?), with suitable reductions, give the best resu lts. evaluations have shown that the best overall performance is achieved using the stencil design shown in followi ng figure. this design is for a stencil thickness of 0.127mm (0.005?). the reduction should be adjusted for stencils of other thicknesses. figure 8-6 stencil pad spacing (all dimensions in mm) 8.3 marking information figure 8-7 marking information
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 38 rev 3.0 08/20/2016 8.4 package information figure 8-8 package dimensions
ir3883 sup ir buck ? synchronous buck regulator layout recommendations datasheet 39 rev 3.0 08/20/2016 figure 8-9 package dimensions table 8.5 environmental qualifications ? ? qualification standards can be found at infineon web site: www.infineon.com table 8-1 environmen tal qualifications ? qualification level industrial moisture sensitivity level pqfn 3 mm x 3 mm jedec level 1 @ 260c esd human body model (jesd22-a114f) class 2 2000v to < 4000v charged device model (jesd22-c101f) class c3 1000v rohs compliant yes
ir3883 sup ir buck ? synchronous buck regulator datasheet 40 rev 3.0 08/20/2016 revision history: revision / date subjects (major changes since previous revision) i ir3883 rev 3.0, 08/20/2016 3.0 08-20-16 ? 1st release to web (production version) ? changed ocp limits based on characterization data (compared with prelim datasheet) ? changed cdm from jesd22-c101d class 3 (<1000v) to jesd22-c101f class c3 ( 1000v) ? added 5v efficiency curves & ocp vs vcc curve
ir3883 sup ir buck ? synchronous buck regulator datasheet 41 rev 3.0 08/20/2016 edition 08/20/2016 published by infineon technologies ag 81726 munich, germany ? 2016 infineon technologies ag all rights reserved. legal disclaimer the information given in th is document shall in no event be rega rded as a guarantee of conditions or characteristics. with respect to any ex amples or hints given herein, any typi cal values stated herein and/or any information regarding the application of the device, infineon technologies hereby disclaims any and all warranties and liabilities of any kind, including wit hout limitation, warranties of non-infringement of intellectual property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com )
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